Multi-layer PCBs are used in a variety of electrical, electronic and optoelectronic applications for mounting and electrically interconnecting electrical, electronic and/or optoelectronic components. A typical multi-layer PCB comprises layers of organic dielectric substrate material, typically referred to as prepreg, having layers of metal embedded therein that are often patterned to provide electrical signal routing. The metal layers are often interconnected by electrically-conductive vias to allow the electrical signals to be routed vertically through multiple layers of the PCB.
A typical multi-layer PCB manufacturing process is a build-up process in which the layers are built one layer at a time. The build-up process typically comprises using dry dielectric film masking steps to selectively mask regions of a metal seed layer disposed on a starting structure, electroplating onto the unmasked regions of the metal seed layer to form a patterned metal layer, removing the dry dielectric film layer and the metal seed layer below it, laminating a layer of dielectric prepreg material on top of the patterned metal layer, drilling one or more via holes through the laminated dielectric prepreg, cleaning the via holes, forming a metal seed layer on the walls of the via holes, and electroplating metal onto the via holes and onto the non-masked areas of the seed layer to simultaneously fill the via holes with metal and form the patterned metal layer. The process is then repeated to form each additional PCB layer.
In many multi-layer PCBs, the electrical signal routing is often separated into radio frequency (RF) signal routing and digital signal routing. A metal electrical isolation layer is typically located in between the layers that contain the digital signal routes and the layers that contain the RF signal routes in order to electrically isolate them from one another to prevent electrical crosstalk between them. An electrical ground layer for the PCB is typically located in a layer beneath the layer that contains the digital signal routes. In other words, the layer that contains the digital signal routes is sandwiched in between the PCB layer that contains the metal electrical isolation layer and the PCB layer that contains the metal ground layer.
FIGS. 1A-1H illustrate cross-sectional views of a plurality of layers of a multi-layer PCB as they are being built up during the aforementioned known fabrication process. With reference to FIG. 1A, a first PCB layer is shown that includes a first metal layer 2 and a first dielectric material layer 3. The first dielectric material layer 3 is typically a layer of prepreg material that is laminated on top of the first metal layer 2. The term “prepreg material” denotes a reinforcing fabric made of woven composite fibers that is impregnated with a resin system (e.g., epoxy) that bonds the composite fibers together. The back side of the prepreg laminate that forms the first dielectric material layer 3 is typically covered with a copper foil layer 4. At least one via hole 5 is typically formed through the first dielectric material layer 3 to allow electrical contact to be established between the first metal layer 2 and one or more subsequently formed metal layers (not shown). The first metal layer 2 and the first dielectric layer 3 together form a single layer of the multi-layer PCB. The first metal layer 2 may be patterned or unpatterned, but for exemplary purposes it will be assumed that the first metal layer 2 is an unpatterned electrical ground layer that constitutes the bottom layer of the multi-layer PCB.
With reference to FIG. 1B, a first dry dielectric film is laminated on top of the copper foil layer 4 and patterned by photolithography (i.e., exposed in predetermined locations to radiation and developed away) to form a dielectric film mask 7. With reference to FIG. 1C, an electroplating process is performed to form a patterned metal layer 8 on the exposed areas of the copper foil layer 4, i.e., on the areas of the copper foil layer 4 that are not masked by the dielectric film mask 7. Simultaneously with the formation of the patterned metal layer 8, the via hole 5 is filled with metal. Prior to forming the dielectric film mask 7, patterning metal layer 8 and filling the via hole 5, an electroless process is performed to deposit a thin layer of metal on the surfaces of the via hole 5 so that the metal that is subsequently electroplated will adhere to the surfaces of the via hole 5. For ease of illustration, the electroless process is not depicted.
With reference to FIG. 1D, after the patterned metal layer 8 is formed and the via hole 5 is filled, the dielectric film mask 7 is stripped off and the copper foil layer 4 is etched away. For exemplary purposes, it will be assumed that the patterned metal layer 8 is the digital signal routing, or redistribution, layer of the multi-layer PCB. With reference to FIG. 1E, a second dielectric material layer 11, that is also a prepreg laminate layer having the same metal-to-metal thickness as the first dielectric material layer 3, is then laminated on top of the patterned metal layer 8. The back side of the prepreg laminate layer has a copper foil layer 12 on it that is identical to copper foil layer 4.
With reference to FIG. 1F, a via hole 14 may be laser-drilled into the second dielectric material layer 11. With reference to FIG. 1G, a second dry film dielectric layer is laminated on top of the copper foil layer 12, exposed to radiation and developed away, leaving a dielectric film mask 15 on top of the copper foil layer 12. With reference to FIG. 1H, a patterned third layer of metal 17 is then electroplated onto the non-masked areas of the copper foil layer 12, including in the via hole 14. For exemplary purposes, it will be assumed that the patterned third layer of metal 17 is the aforementioned electrical isolation metal layer that electrically isolates the digital routing layer 8 from one or more RF signal routing layers (not shown) that are on the opposite side of the electrical isolation metal layer 17 from the digital routing layer 8.
The process described above with reference to FIGS. 1A-1H continues until the PCB has the intended number of PCB layers. Each PCB layer, as that term is used herein, includes a layer of metal, which may or may not be patterned, and a layer of prepreg that is laminated onto the layer of metal. Thus, in FIG. 1H, the first metal layer 2 and the first dielectric material layer 3 together constitute a first PCB layer and the second metal layer 8 and the second dielectric material layer 11 together constitute a second PCB layer.
One of the difficulties associated with this type of PCB design process is that if additional digital signal routing is needed to interconnect (i.e., cross overs of traces) digital signal routes of metal layer 8, an additional PCB layer must be added between the aforementioned second and third PCB layers because the digital signal routes cannot be routed into the layer above the electrical isolation layer 17 or below the metal ground layer 2, which is typically the bottom surface of the PCB that serves as an interface between the PCB and external circuitry of a motherboard. Adding additional PCB layers may not be possible or practical due to total thickness requirements of the PCB and/or due to cost constraints. At the same time, there is a counter-challenge in the PCB manufacturing industry to decrease costs and total PCB thickness.
Accordingly, a need exists for a way to increase routing flexibility in multi-layer PCBs without increasing the total number of traditional layers of the PCBs, the total thickness of the PCBs or the PCB manufacturing costs.